1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device wherein a plurality of memory cells are connected to form memory cell units.
2. Description of the Related Art
Conventionally, as one of the semiconductor memory devices, there have been known EEPROMs, which are capable of electrically rewriting. Among the EEPROMs, there has been noticed an EEPROM called NAND cell type wherein a plurality of memory cells are connected in series to form a unit one end of which is connected to a bit line and a high integration can be attained.
One memory cell of the NAND cell type EEPROM comprises an FETMOS structure in which a floating gate (charge storage layer) and a control gate are layered on a semiconductor substrate through an insulating film, and an NAND cell is formed, and a plurality of memory cells are connected in series in a form that the plurality of the adjacent memory cells use a source and a drain in common. Such NAND cells are arranged in a matrix array, so that a memory cell array is formed.
A drain which is one end of each of the NAND cells arranged in an array direction of the memory cell array is connected in common to a bit line through a select gate transistor, and a source which is the other end is connected to a common source line through another select gate transistor. Control gates of memory transistors and gate electrodes of select gate transistors are connected in common to each other in a column direction of the memory cell array, each serving as a control gate line (word line) and a select gate line.
An operation of the NAND cell type EEPROM will be explained as follows.
Data writing is executed in order from the memory cell which is far from the bit line. In the case of n channel, high voltage (for example 20 V) is applied to the control gate of the selected memory cell, and an intermediate voltage (for example 10 V) is applied to the control gate of the non-select memory cell which is on the side of the bit line, and the gate of the select gate transistor. 0V (for example "1") or an intermediate voltage (for example "0") is applied to the bit line according to data. At this time, the voltage of the bit line is transmitted to the channel of the select memory cell through the select gate transistor and the non-select memory cell.
when there is data to be written (data is "1"), a high electrical field is applied between the gate and channel of the select memory cell, and an electron is tunnel-injected to the floating gate from the substrate. Thereby, a threshold value of the select memory cell is moved in a positive direction. When there is no data to be written (data is "0"), the threshold value is unchanged.
For erasing data, high voltage is applied to a p-type substrate (an n-type substrate in a case of a well structure and a p-type well formed thereon), and the control gate of all memory cells and the gate of the select gate transistor are set to 0 V. Thereby, in all memory cells, the electron of the floating gate is emitted to the substrate, and the threshold value is changed to a negative direction.
For reading data, the select gate transistor and non-select memory cell other than the select memory cell are turned on, and 0 V is applied to the gate of the select memory cell. At this time, current flowing to the bit line is read, thereby discriminating between "0" and "1 ."
In such a conventional NAND cell type EEPROM, there is a problem in a mismatch of delay time of the control gate in data reading or writing, that of delay time of rise of the select gate and that of delay time of fall of the select gate.
For example, in the case of an NAND cell type EEPROM of 32M bits, if a width of one control gate line is 0.5 .mu.m, a length thereof is 7500 .mu.m, a sheet resistance p is 70.OMEGA. per 1 .mu.m.times.1 .mu.m, a resistance is 1050 k.OMEGA., approximately 1 M.OMEGA.. Also, a capacity is 4.5 PF, and its CR time constant is CR=4.5 PF.times.1 M.OMEGA.=4.5 .mu.S. In SPICE simulation, the build up time of the control gate line results in 7.0 .mu.S up to 90% of power supply voltage Vcc.
FIG. 1 shows a layout of a core section of conventional 4M bit, 16M bit, and 32M bit NAND cell type EEPROMs. BL0 to BLm are bit lines, CGN1 to CGN8: control gate lines, SGN: a drain side select gate line, and SGS is a source side select gate line.
As shown in the FIG. 1, control gate lines (odd numbers) CGN1, CGN3, CGN5 and CGN7, and the drain side select gate line SGN are controlled by driver odd circuits arranged at the left side of the FIG. 1. The control gate lines (even numbers) CGN2, CGN4, CGN6 and CGN8, and the source side select gate line SGS are controlled by driver even circuits arranged at the right side of the FIG. 1.
The reason why the driver circuits to the NAND cell group of the same row are divided into the even circuits and the odd circuits is that a drive element for one control gate line cannot be provided in the pitch of the control gate line.
FIG. 2 shows the specific structure of the first decoder circuit, the driver circuits, and the NAND cell columns, of the core section of the NAND type EEPROM of FIG. 1.
At the time of the reading operation, for example, in a case where the control gate line CGN3 is selected, data of the memory cells Cellj30 to Cellj3m, which are connected to CGN3 is read to the bit lines BL0 to BLm, the control gate line CGN3 is charged to the ground voltage Vss (0 V), and the other control gate lines CGN1, CGN2, CGN4 to CGN8, and the select gate lines SGN and SGS are charged to the power supply voltage Vcc (5 V).
In this case, the driver circuits of the control gate lines and the select gate lines are arranged to be divided right and left, and the CR constants of the control gate lines and the select gate lines are high, i.e., 4.5 .mu.S. Due to this, there is a problem in that timing of charging/discharging does not coincide with each other between the odd and even control gate lines, and the select gate lines of the drain side and the source side.
More specifically, for example, Cellj10 to Cellj80, which are connected to the BL0, will be explained as follows.
The control gate lines (odd numbers) CGN1, CGN5, CGN7 and the drain side select gate line SGN are charged to 5 V by the driver odd circuit nearest the Cellj10 to Cellj80. At this time, the control gate lines (even numbers) CGN2, CGN4, CGN6, CGN8 and the source side select gate line SGS are charged to 5 V by the driver even circuit farthest from the Cellj10 to Cellj80.
As explained above, in the same NAND cell, if the driver circuits of the control gate lines and the select gate lines are arranged to be divided right and left, there is a problem in that timing of charging/discharging does not coincide with each other in the odd and even control gate lines of the same NAND cell. In the case of, e.g., the 32M bit NAND cell type EPROM, the line pitch of the control gate line is 1.05 .mu.m (line width 0.55 .mu.m/space 0.50 .mu.m), the driver circuit for one control gate line cannot be provided in this pitch. Due to this, it is needed that the driver circuits be divided right and left.
Moreover, according to the conventional NAND cell type EEPROM, an output signal CLKALj,/CLKAj of the decoder circuit are inputted to both driver odd circuits on left side and driver even circuits on right side. Due to this, the output signals CLKAj,/CLKAj must run on the memory cell array, and there occurs a problem in that a resistance capacitance is increased by the large wire length. Due to this, there is generated a time difference in the timing for inputting the output signals CLKAj,/CLKAj of the decoder circuit to the driver odd circuits on left side and the driver even circuits on right side, a and high speed reading operation is prevented by the time difference.
Furthermore, since the wiring of the output signals CLKAj,/CLKAj is formed to cross the right and left of the memory cell array, it is needed that a wiring layer be formed to be different from the control gate lines, select gate lines, and the bit lines. More specifically, in a case where the floating gate uses polysilicon of the first layer, the control gate line and the select gate line use polysilicon of the second layer, the wiring of the output signals CLKAj,/CLKAj is formed of A1 if the bit line uses polysilicon of the third layer. Reversely, if the wiring of CLKAj,/CLKAj uses polysilicon of the third layer, the bit line is formed of A1. In this way, in the conventional NAND cell type EEPROM, since the wiring of the output signals CLKAj,/CLKAj is formed to cross the right and left of the memory cell array, three polysilicon layers and one Al layer are needed.
Then, as shown in FIG. 3, as a decoder circuit, if row decoders r are provided to the right of the memory cell array, and row decoders 1 to the left respectively, there is no need that the wiring of the output signals CLKAj,/CLKAj is formed to cross the right and left of the memory cell array. However, in this case, the number of the decoder circuits is doubled, and the chip area is increased, and an increase in the manufacturing cost is brought about.
Moreover, at the time of the writing operation, for example, in a case where the control gate line CGN8 is selected, data is written to the memory cells Cellj80 to Celli8m, which are connected to CGN8, the control gate line CGN8 is charged to a high voltage Vpp (20 V), and the other control gate lines CGN1 to CGN7, and the drain side select gate line SGN are charged to an intermediate voltage Vm (10 V). Even in the writing operation, according to the layout of the conventional NAND cell type EEPROM of FIGS. 1 and 2, there is also a problem in that a time difference is generated in odd and even control gate lines of the same NAND cell and the select gate lines of the drain side and the source side from the left driver odd circuits and the right driver even circuits.
According to the conventional semiconductor memory device, a spare memory cell array is provided to save a defective bit when an input address and an address of a defective cell are conformed to each other, the word line of the spare memory cell array is selected, and the defective cell is replaced with a spare cell.
In such a defective bit saving, as shown in FIG. 3, according to the structure in which the word line drivers and the row decoders are provided at both sides of the memory cell array, in a case where a defect such as a short-circuit between the word lines is generated between two adjacent word lines, the row decoders of both sides must be saved. In other words, the defective saving must be performed with low efficiency, such as one defect is saved by two row decoders.
As mentioned above, according to the conventional NAND cell type EEPROM, the drivers of the same NAND cell are divided into the driver even circuits and the driver odd circuits at the right and left of the memory cell array because of the limitation of the pitch of the control gate line. Due to this, there is the problem as follows.
More specifically, there is generated the time difference between charging/discharging in the odd and even control gate lines of the same NAND cell and the select gate lines of the drain and the source side, and the reading and writing operations becomes unstable, and reliability is reduced.
Moreover, according to the conventional NAND cell type EEPROM, since the output signals of the decoder circuits are inputted to both left driver odd circuits and right driver even circuits, the output signals must run on the memory cell array. Due to this, there is the problem as follows.
More specifically, one wiring layer of the output signal of the decoder circuit is needed, and the manufacturing cost is increased.
Furthermore, if the decoder circuit is provided at both sides of the memory cell array, the number of the row decoders is doubled. Due to this, the chip area is increased.
Moreover, in the structure in which the word line drivers and the row decoders are provided at both sides of the memory cell array to be driven from each side every word line, there is a problem that the saving efficiency of the defective bit is low.
Moreover, conventionally, since the driver circuit of the word lines of even numbers and that of the word lines of odd numbers, which are provided in the same cell unit, were separated into right and left sides, both side driver circuits had to be selected at the time of the operation. Due to this, since a high voltage (voltage boosted in the chip, which is necessary to erase/write data of the memory cell, must be applied to both right and left driver circuits, there occurred problems in which a load capacity of a voltage booster circuit is large, an area of the voltage booster circuit is increased, and data erasing/writing time is increased.
The above-mentioned problems are not limited to the NAND cell type EEPROM. The same problems occur in the semiconductor memory device such as a DINOR cell type EEPROM having the memory cell array comprising a plurality of memory cells connected in parallel, and an AND cell type EEPROM. Moreover, it is not limited that the above problems occur in the semiconductor memory device using a nonvolatile memory cell. It can be said that the same problems occur in the semiconductor memory device using a dynamic type cell. Furthermore, it is not limited that the above problems occur in the semiconductor memory device having memory cell units. It can be said that the same problems occur in the semiconductor memory device in which the memory cells are arranged in an array form.